A conventional computer system will be described below by referring to Japanese Laid Open Patent Application (JP-P2005-215809A: a first related art). The computer system described in the first related art contains a processor, an IO control circuit, a PCI bus and a memory (main storage). The processor is connected to the IO control circuit. The memory is connected to the processor and the IO control circuit. The memory stores an OS (Operating System) that includes a driver. The PCI bus is connected to the IO control circuit. A plurality of peripheral devices are connected to the PCI bus.
The processor issues an operation transaction for the PCI bus, in order to execute a job. In this case, the processor outputs the operation transaction through the IO control circuit to the PCI bus. For example, when a failure has occurred on the PCI bus, the IO control circuit sets a bus failure indicator (a closing flag) and closes the PCI bus.
In this case, the processor issues an operation transaction for the PCI bus. In this case, since the closing flag is set, the 10 control circuit generates a closed transaction indicating that the PCI bus has been closed, in response to the operation transaction, and outputs (replies) to the processor. The closed transaction has all bits of “1” (referred to as ALL1) and is represented by FFFFFFFFh in case of a 4-byte data. The processor can determines that the failure has occurred on the PCI bus, because the closed transaction indicating the ALL1 is returned in response to the operation transaction.
When the closed PCI bus is recovered, the IO control circuit releases the closing flag. In this case, the processor again issues an operation transaction for the PCI bus, in order to execute the job. Consequently, in the first related art, even if the failure has occurred on the PCI bus, a recovering and continuing operation is performed, and an error recovery can be attained without any stop of the computer system.
However, in the computer system described in the first related art, the PCI bus is directly connected to the IO control circuit. For this reason, there are the following problems.
When a device connected to the PCI bus is a bridge or switch, there may be a case that one or a plurality of PCI buses are connected to the device. In such a case, if the failure has occurred on the PCI bus in the bridge or switch, the IO control circuit cannot recognize the PCI bus to be closed. In this way, when the device is connected to the IO control circuit and the plurality of PCI buses are connected to the device, the computer system of the first related art cannot close the PCI bus on which the failure has occurred.
Generally, the PCI bus can adopt a bus configuration. However, when a plurality of devices are mounted on the bus, an operational frequency cannot be made high due to electric problems such as the increase in load capacity on a bus and a clock skew. Thus, in recent years, one device is connected to one bus, as in PCI Express, to improve the performance in many cases. However, this method uses the number of the slots. Thus, it is required that many PCI slots are ensured by connecting a PCI bridge or a PCI Express switch to increase buses. General cheap parts are used as the bridge and the switch in many cases. However, the functions described in the first related art are not mounted in the bridge and the switch. Therefore, when an error recovery is to be realized, the general bridge and switch cannot be used.